The present invention relates to bias circuits, and more particularly to an interactive bias circuit for reading non-volatile memory elements.
Many electronic systems include memory devices. The memory devices are often used to store critical information that is needed by the electronic system. In some instances it is necessary for the memory device to provide non-volatile storage. Non-volatile memories allow for information to be permanently or semi-permanently stored such that removing power from the memory does not destroy the stored information. Example non-volatile memory devices include Erasable Programmable Read Only Memory (EPROM) as well as others.
The trend in the electronics industry is to reduce overall power consumption in electronic systems. This trend is largely due to the proliferation of battery powered electronic systems. In an effort to preserve battery life, battery powered devices require their electronics to consume less power under operation. Because electronics are often disabled to conserve power, non-volatile memory devices are well suited to preserve any critical information required by the electronics.
Non-volatile memories often require a significant amount of power during operation. This is partially due to a bias circuit that is employed to bias the non-volatile memory during operation. In order to reduce power consumption, the bias circuit is disabled until operation is required. When the electronic system is ready to read or write to the non-volatile memory, the associated bias circuit is enabled.
In order to correctly read the memory device, a correct bias voltage must be available for use by the memory device. When the associated bias circuit is first enabled, the bias voltage may not be available until the biasing circuit reaches a steady-state operating condition. After the associated biasing circuit reaches the steady-state operating condition the memory device can be correctly accessed. Therefore, the memory device should not be read until the correct biasing voltage is available.
Many bias circuits implement an open-loop delay using one-shot circuits or capacitor timing type delay circuits that are designed to handle a worst-case delay. By designing the open-loop delay to handle a worst-case delay, the bias circuit ensures that the correct bias voltage is reached before reading the memory element. Typically, these bias circuits are tailored to the processing environment and need to be re-designed when the number of memory elements changes or when the processing environment changes.
The present invention provides an interactive bias circuit that dynamically determines when the bias circuit has reached a steady-state operation without adding xe2x80x9cartificialxe2x80x9d margins to compensate for temperature variations, process variations and power supply ranges. In addition, because the interactive bias circuit determines the actual condition of the bias circuit, the interactive bias circuit may be reused without redesigning the bias circuit when additional memory elements are added.
In one embodiment, the interactive bias circuit includes a read enable circuit, a bias circuit, and an output circuit. The read enable circuit is configured to provide a read enable signal, such as when power-on is detected. The bias circuit provides a read signal in response to the read enable signal and a memory element bias voltage. The read signal is in a first state when the memory element bias voltage is a non-final voltage and the read signal is in a second state when the memory element bias voltage is a final voltage. The bias circuit is configured to dynamically detect when the memory element bias voltage is at the final voltage. The memory element bias voltage transitions from the non-final voltage to the final voltage based on the loading of the memory elements (e.g., EPROMs) on the bias circuit. When the memory element bias voltage obtains the final voltage, the bias circuit outputs a read signal that initiates reading of data stored in the memory elements. The output circuit is configured to detect when the memory elements have been read using the read enable signal and the output data generated from the memory elements. The output circuit may further be configured to signal the read enable circuit to remove the read enable signal, thus ending a read cycle of the memory elements.
In one aspect of the invention, the output data includes a first output and a second output for each of the memory elements. The first output and second output correspond to a charge that is stored in the memory element. The output circuit detects when the memory elements have been read based on the first and second output of one of the memory elements.
In another aspect of the invention, the bias circuit includes a bias generator, a memory element driver and a detector. The bias generator is configured to generate an internal bias voltage that is provided to the memory element driver and the detector. The memory element driver produces the memory element bias voltage in response to the internal bias voltage and is configured to produce a sense current that is responsive the memory element bias voltage such that the sense current varies with the memory element bias voltage. The detector is configured to produce a reference current. The reference current may be substantially similar to a memory element current that flows through one of the memory elements during the reading of the memory element. The detector also generates the read signal based on a comparison of the reference current with the sense current. The sense current may be increased by a pre-determined factor before the comparison of the reference current with the sense current in order to ensure accuracy for the read signal.
In still another aspect of the invention, the bias circuit may further include a feedback suppression logic. The feedback suppression logic is configured to suppress feedback from the memory elements that affect the read signal.
In another embodiment of the invention, a method of reading memory elements of an electronic device is provided. The method includes enabling a bias circuit that activates a read operation of the memory elements within the electronic device. Once the bias circuit is activated, a reference current is generated. The reference current corresponds to a memory element current within one of the memory elements that occurs during the read operation. In addition, a sense current is produced. The sense current varies in accordance with the loading of the memory elements on the bias circuit. The reference current and the sense current are compared and when the difference is within a pre-determined threshold, a memory read of the memory elements is initiated. Once the memory read of the memory elements has completed, the bias circuit is disabled.
In one aspect of the invention, the sense current is increased by a predetermined factor before comparing the reference current with the sense current.
In another aspect of the invention, producing a sense current includes detecting the loading of the memory elements on the bias circuit. The loading of the memory elements produces a bias voltage. The sense current varies in relation to the changing bias voltage. The difference between the reference current and the sense current will be within the pre-determined threshold once the bias voltage obtains a final bias voltage. The final bias voltage provides adequate voltage to each of the memory elements to ensure a successful memory read.
In yet another embodiment of the invention, an interactive bias circuit for reading a plurality of non-volatile memory elements is provided. The interactive bias circuit includes a power-on sensing means, a generator means, a memory element replica means, a detector means and an output means. The power-on sensing means provides a read enable signal upon sensing that power is available to the interactive bias circuit. Upon detecting the read enable signal, the generator means generates a bias voltage that is used by the memory element replica means and the detector means. The memory element replica means produces a sense current upon detecting the read enable signal. The sense current varies in accordance with a loading associated with the non-volatile memory elements. The memory element replica means also provides a memory element bias voltage to the non-volatile memory elements that allows reading to occur. The detector means produces a reference current upon detecting the read enable signal. The reference current is substantially similar to a memory element current resident in the memory elements during a read operation. The detector means may further detect when the sense current and the reference current are within a pre-determined threshold. Once the sense current and reference current are within the predetermined threshold, the detector means provides a ready signal to the non-volatile memory elements. The ready signal initiates the read operation within the non-volatile memory elements. The output means detects when the read operation has completed and signals the power-on sensing means to remove the read enable signal, thus, completing a read cycle.
In one aspect of the invention, the interactive bias circuit may further include a feedback suppression means. The feedback suppression means suppresses feedback from the memory elements that affect the ready signal.
In another aspect of the invention, the generator means includes a current source that produces the bias voltage used by the memory element replica means and the detector means.
In still another aspect of the invention, the memory element replica means includes a first and second diode connected transistor in series. The first diode connected transistor couples to a power supply voltage and the second diode connected transistor couples to a first node. The memory element bias voltage is provided at the first node.
In yet another aspect of the invention, the memory element replica means further includes a switching transistor. The switching transistor is coupled to the power supply voltage and the first node. The memory element bias voltage is maintained at the power supply voltage by the switching transistor until the read enable signal becomes active.
In still yet another aspect of the invention, the detector means includes two diode-connected transistors in series, a first current mirror, and a second current mirror. The reference current is reflected by the first mirror into the second mirror. The second mirror reflects the reference current into a second node. When the sense current overcomes the reference current at the second node, the ready signal becomes active.
In still a further aspect of the invention, the detector means further includes a switching transistor. The switching transistor is coupled to the second mirror at the second node and is configured to receive the read enable signal. The switching transistor maintains the ready signal at a first state until the read enable signal becomes active.